We specialize in the independent verification of Solid State Interlocking (SSI) data source code and free-wired route relay interlocking (RRI). We can also verify the following designs:
- Minor Signalling Scheme Plans and Sketches;
- Aspect Sequence Charts;
- Control Tables;
- Computer Based Interlocking (CBI);
- ‘Westpac’ Mk IV Geographical Interlocking;
- Electro-Mechanical Interlocking.
Where the engineering framework for the project is already established:
- Level Crossing Details;
- Lineside Location Details;
- Signalling Specifications.
Problem solving and novel or new applications:
- Functional development of signalling relay circuits;
- Functional development of data constructs.
